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TGF4118-EPU
18 mm Discrete HFET
4118
* * * * *
0.5 um gate finger length Nominal Pout of 9.0 Watts at 2.3 GHz Nominal PAE of 53% at 2.3 GHz Nominal Gain of 11.5 dB at 2.3 GHz Die Size 36.0 x 81.0 x 4.0 mils (0.914 x 2.057 x 0.102 mm)
TGF4118-EPU RF Performance at F = 2.3 GHz Vd = 8.0 V, Vg = -1.1 V, Iq = 1.69 A and T A = 25C
50 Pout 48 46 PAE 50 45 44 42 40 38 36 25 34 32 30 20 22 24 26 28 30 32 20 15 40 35 30 55
Input Power (dBm)
Power Added Efficiency %
1
TriQuint Semiconductor Texas Phone: 972 994-8465
Output Power (dBm)
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TGF4118-EPU RF Performance for Vd = 7.0 V, F = 2.3 GHz, and TA = 25 C Quiescent Id is 1.74 A (Vg = -1.1 V), 1.37 A (Vg = -1.3 V), and 1.02 A (Vg = -1.5 V)
130 120 Predicted Channel Temp (C) 110 100 90 80 Tch 70 60 Pout 50 40 30
60 55 Power Added Efficiency % 50 45 40 35 30 25 20 15 Vg = -1.1 V Vg = -1.3 V Vg = -1.5 V
42 41 40 39 38 37 36 35 Vg = -1.1 V Vg = -1.3 V Vg = -1.5 V 34 33 32 Output Power (dBm)
2
15 14 13 Gain (dB) 12 11 10 9 8 7 20 Vg = -1.1 V Vg = -1.3 V Vg = -1.5 V 21 22 23 24 25 26 27 Input Power (dBm) 28 29 30 31
TriQuint Semiconductor Texas Phone: 972 994-8465
Fax 972 994-8504
Web: www.triquint.com
TGF4118-EPU RF Performance for Vd = 8.0 V, F = 2.3 GHz, and TA = 25 C Quiescent Id is 1.69 A (Vg = -1.1 V), 1.38 A (Vg = -1.3 V), and 1.06 A (Vg = -1.5 V)
140 130 Predicted Channel Temp (C) 120 110 100 90 80 Pout 70 60 50 40
60 55 Power Added Efficiency % 50 45 40 35 30 25 20 15 15 Vg = -1.1 V Vg = -1.3 V Vg = -1.5 V
42 41 40 39 38 Tch 37 36 35 Vg = -1.1 V Vg = -1.3 V Vg = -1.5 V 34 33 32 Output Power (dBm)
3
14 13 Gain (dB) 12 11 10 9 8 20 Vg = -1.1 V Vg = -1.3 V Vg = -1.5 V 21 22 23 24 25 26 27 Input Power (dBm) 28 29 30 31
TriQuint Semiconductor Texas Phone: 972 994-8465
Fax 972 994-8504
Web: www.triquint.com
TGF4118-EPU RF Performance for Vd = 9.0 V, F = 2.3 GHz, and TA = 25 C Quiescent Id is 1.66 A (Vg = -1.1 V), 1.39 A (Vg = -1.3 V), and 1.09 A (Vg = -1.5 V)
160 150 Predicted Channel Temp (C) 140 130 120 110 100 90 Pout 80 70 60
55 50 Power Added Efficiency % 45 40 35 30 25 20 15 10 15 Vg = -1.1 V Vg = -1.3 V Vg = -1.5 V
42 41 40 39 Tch 38 37 36 35 Vg = -1.1 V Vg = -1.3 V Vg = -1.5 V 34 33 32 Output Power (dBm)
4
14 13 Gain (dB) 12 11 10 9 8 20 Vg = -1.1 V Vg = -1.3 V Vg = -1.5 V 21 22 23 24 25 26 27 Input Power (dBm) 28 29 30 31
TriQuint Semiconductor Texas Phone: 972 994-8465
Fax 972 994-8504
Web: www.triquint.com
DC Characteristics for the TGF4118-EPU
DC probe Parameters IDSS GM VP BVGS BVGD Drain Saturation Current Transconductance Pinch Off Voltage Breakdown Voltage Gate-Source Breakdown Voltage Gate-Drain Nominal 4410 2970 -1.85 -22 -22 Unit mA mS V V V
Example of DC I-V Curves Vg = 0.0 V to -2.75 V in 0.25 steps TA = 25 C
4500 4000 3500
Drain Current (mA)
3000 2500 2000 1500 1000 500 0 0 1 2 3 4 5 6 7 8 9
D r a in V o l t a g e ( V )
Absolute Maximum Ratings
Drain-to-source Voltage, Vds................................. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ..........12 V Gate-to-source Voltage, Vgs..................... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .............-5 V to 0 V Mounting Temperature.................... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... ............ ... ... ... ... ... 320C Storage Temperature........................ ... ... ... ... ... ... ... ... ... ... ... ... ... .... ................ -65C to 200C Power Dissipation.............. ... ... ... ... .... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ..refer to Thermal Model Operating Channel Temperature... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... .refer to Thermal Model
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in this document is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
TriQuint Semiconductor Texas Phone: 972 994-8465
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5
TGF4118-EPU Linear Model Vds = 7 V and Ids = 1.24 A at T = 25 C
FET Elements Lg = .00176 nH Rg = 0.42115 Rgs = 5447 Ri = .05082 Cgs = 18.82602 pF Cdg = 1.03674 pF Rdg = 13600 Rs = 0.06265 Ls = 0.00869 nH Rds = 6.40925 Cds = 3.72019 pF Rd = 0.01831 Ld = 0.00195 nH VCCS Parameters M = 2.04398 S A=0 R1 = 1E19 R2 = 1E19 F=0 T = 4.5116 pS Cdg
Rdg Lg G Ri Rgs R1 Cgs R2 Rds Cds Rg VCCS Rd Ld D
Rs
Ls
Freq-GHz MAG-S11 ANG-S11 MAG-S21 ANG-S21 MAG-S12 ANG-S12 MAG-S22 ANG-S22 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.96061 0.96275 0.96332 0.9637 0.96407 0.96446 0.96488 0.96532 0.96579 0.96628 -157.13 -168.492 -172.363 -174.323 -175.515 -176.325 -176.917 -177.374 -177.743 -178.05 4.44294 2.25188 1.49968 1.11963 0.88979 0.73541 0.62432 0.54038 0.47464 0.42171 98.2855 88.8751 83.3713 78.9074 74.9064 71.1835 67.6655 64.3208 61.1349 58.1017 0.00932 0.00949 0.00955 0.00962 0.00971 0.00985 0.01003 0.01028 0.01058 0.01096 14.7392 13.5187 15.8589 19.1829 22.9596 26.9945 31.1758 35.4143 39.6273 43.7382 0.85196 0.85594 0.85818 0.86065 0.86355 0.86689 0.8706 0.87462 0.87887 0.88328 -178.271 -178.561 -178.438 -178.22 -177.98 -177.746 -177.53 -177.338 -177.174 -177.04
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6
Thermal Model of TGF4118-EPU
Predicted Channel Temperature vs Base Plate Temperature 250 240 230 220 210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 25
With a .020" CM15 (15/85 Copper Molybdenum) carrier plate solder attached using 0.0015" AuSn (80/20) solder
Channel Temperature (C)
Pd = 5 Watts Pd = 10 Watts 35 45 55 65 75 85 95 105 115 125
Base Plate Temperature (C) Tc = 2.052 + 6.796 x Pd + 0.1465 x Pd 2 + (1.002 + 0.01999 x Pd + 0.0002725 x Pd 2) x Tbase (Predicted Channel Temperature equation for the given assembly stack up) This model assumes perfect solder connections (no voids) between the FET and the carrier plate.
HFETChannel Temperature vs Median Life 350
Channel Temperature (C)
300
250
200
150
100 0 1 2 3 4 5 6 7 8 9 10 Median Life (10^X Hours)
TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com 7
Mechanical Drawing of TGF4118-EPU
81.0 (2.057) 76.3 (1.938) 69.0 (1.753) 61.6 (1.565)
65.3 (1.659)
48.8 (1.239)
52.5 (1.333) 45.1 (1.145)
32.2 (0.819)
35.9 (0.913) 28.5 (0.725)
15.7 (0.399)
19.4 (0.493) 12.0 (0.305)
4.7 (0.119) 0.0
0.0
7.4 (0.187)
24.9 (0.632)
36.0 (0.914)
Alternate gate pad
Alternate drain pad
Units: mils (mm) Thickness: 4.0 (0.10) Gate pad sizes are 4.0 x 4.0 (0.10 x 0.10) Drain pad sizes are 4.7 x 14.5 (0.12 x 0.37) A minimum of four gate bonds and eight drain bonds is recommended for operation. Sources are connected to backside metalization. Alternate gate and drain pads are located on either end of the FET for paralleling TGF4118-EPUs.
Drain
Gate
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8
Application circuit for the TGF4118-EPU at 2.3 GHz
The FET is soldered using AuSn solder at 300 C for 30 secs. Input and Output matching networks are 0.381 mm ZrSn Tioxide substrates (Er = 38). The design load impedance is between 4 and 5 with the 6 pF output capacitance of the FETincluded in the output network. For further explanation refer to the application note " Designing High Efficiency Amplifiers using HFETs" The carrier plate is 0.51 mm . gold plated copper molybdenum. Gold wire (0.018 mm) is used for the bonds. Four gate bonds are required with a length of 0.42 mm. Eight drain bonds are required with a length of 0.42 mm. Bondwire end points on the FET are in the middle of the bond pads. Refer to the figures above for bondwire locations. Connection between the 50 ohm line input to the input match is made by a parallel RC network. R1 in this network is 10 ohms, and C1 is 5.6 pF. The components used are surface mount 0603 piece parts.
9
TriQuint Semiconductor Texas Phone: 972 994-8465
Fax 972 994-8504
Web: www.triquint.com

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